In many solid-state imagers, a parallel array of CCD charge transfer channels stores charge packets descriptive of respective elements of an image. These elements are termed "pixels", a contraction of the phrase "picture elements". The storage of the pixels is in a column and row array, with the rows corresponding to lines of scan in the raster-scanned sample-data video output signal.
There are two basic ways to arrange the parallel array of CCD charge transfer channels, in order to facilitate the sequential transfer of the charge packets to charge sensing circuitry for their conversion to respective samples of the raster-scanned video output signal. The seemingly more natural of the two ways is to align the lengths of the charge transfer channels with the rows of the pixel array and then forward clock the charge transfer channels sequentially, one after the other, to generate raster scan.
However, the way the CCD charge transfer channels are parallelly arranged in most prior-art semiconductor imagers is the other way, with the lengths of the charge transfer channels aligned with the columns of the pixel array. The charge transfer channels are forward clocked in parallel to transfer out charge packets parallelly by row, during line retrace intervals in the raster-scanned sample-data video output signal of the solid-state imager. It is customary to load each row of charge packets transferred out parallel-in-time to respective charge transfer stages of an output CCD line register, while halting the forward clocking of that output CCD line register during its loading. (This procedure of loading directly into an intermediate charge transfer stage is referred to as "side-loading".) Then, during the line trace interval, the output CCD line register is forward clocked to transfer the charge packets serially to charge sensing circuitry for conversion to respective samples of a line of the raster-scanned video output signal. The differential time delay in the CCD circuitry for removing charge packets from successive columns of the pixel array presents no problem, because it accords with the need for providing differential time delay of successive pixels in each scan line when generating raster-scanned video signal.
The seemingly more natural method of removing charge packets from the pixel array, a row at a time via a respective charge transfer channel, is described by P. K. Weimer in U.S. Pat. No. 3,683,193 issued Aug. 8, 1972, entitled "BUCKET BRIGADE SCANNING OF SENSOR ARRAY", and assigned to RCA Corporation. Weimer describes a device using photosensors separate from the means for transferring charge packets out of the imager. The means for transferring charge packets out of the imager which Weimer specifically describes is bucket brigade circuitry, but in more modern devices charge coupled device (CCD) circuitry is used instead. These CCD imagers are an interline transfer type, with transfer being in the direction of line scan. Since line scan is customarily in the horizontal direction, these CCD imagers are sometimes referred to as being of horizontal interline transfer type.
CCD imagers which collect photocharge into packets within the row-aligned CCD charge transfer channels themselves are known and are referred to as being line transfer type. Line transfer CCD imagers are described by P. K. Weimer in U.S. Pat. No. 4,242,700 issued Dec. 30, 1980, entitled "LINE TRANSFER CCD IMAGERS", and assigned to RCA Corporation. A line transfer CCD imager has, as its image register, a line-transfer register comprising a parallel array of charge transfer channels disposed in a substrate of semiconductive material, the lengths of which charge transfer channels align with the direction of line scan of the image being televised. To implement line scanning of the image, the charge transfer channels selectively receive dynamic forward clocking signals, usually one charge transfer channel at a time.
The non-selected charge transfer channels receive static clocking signals for inducing a succession of potential barriers in those charge transfer channels. These potential barriers and the channel stops defining the sides of the charge transfer channels define charge collection sites for accumulating charge carriers generated by photoconversion of respective elements (or "pixels") of a radiant energy image impinging on the image register. The accumulation of the charge carriers generated by photoconversion in the charge transfer channels and the portions of the substrate respectively underlying them results in charge packets that sample the intensity of respective pixels of the radiant energy image.
The successive charge packets which sample successive image pixels along a scan line are transferred to a charge sensing stage, or electrometer, for conversion to voltage or current samples of a line of video signal descriptive of a respective line scan of the radiant energy image. The selection of the charge transfer channels to be forward clocked is carried out in a regularly recurrent pattern that defines frame scan.
The frame scan pattern can comprise successive fields in each of which fields each charge transfer channel in the image register is successively selected. Such frame scan pattern does not exhibit field-to-field line interlace.
Frame scan patterns that provide for field-to-field line interlace are also possible. One way to provide field-to-field line interlace is to sequentially forward clock one set of alternate charge transfer channels in the image register during odd-numbered ones of consecutively numbered successive fields of image scan, and to sequentially forward clock the other set of alternate charge transfer channels in the image register during even-numbered fields of image scan. Another frame scan pattern, which provides field-to-field pseudo line interlace, scans successive pairs of image register charge transfer channels, in one of the two possible phasings during odd-numbered fields of image scan, and in the other possible phasing during even-numbered fields of image scan.
The portion of a line transfer CCD imager (or of a CCD imager of related type) which is of concern with regard to the present invention is the CCD circuitry for conveying charge packets from the line-transfer register to the charge sensing stage. In prior art imagers this CCD circuitry includes a CCD shift register, the charge transfer channel of which is perpendicular to the charge transfer channels of the line-transfer register and abuts the ends of the line-transfer register charge transfer channels from which charge packets are transferred by forward clocking. The charge packets, transferred from the line-transfer register charge transfer channel(s) selected for forward clocking, side-load the abutting charge transfer stage(s) of the CCD shift register and are sequentially shifted to the charge sensing stage at the output end of the CCD shift register. Adjacent points in scan lines successively scanned should be separated by a 1 H delay in a normal video signal, 1 H being the combined durations of field trace interval and field retrace interval--i.e., a full line time. Where the successive line scans (in which the line-transfer register charge transfer channels are successively forward clocked) begin a full line time apart, the different delays through the CCD shift register for the charge packet output of each image register charge transfer channel causes the successive lines of charge packets to reach the charging sensing stage at intervals which differ from 1H. The response of the charge sensing stage to these lines of charge packets tends to exhibit a shearing distortion as between the successive lines of video signal. This tendency can be curbed by compensating for the differential time delay through the CCD shift register. This compensation can be provided, for example, by beginning the selective forward clocking of successive charge transfer channels in the image register on intervals progressively shorter than 1H.
There are problems that the line transfer CCD imager with a side-loaded output register has that are sufficiently serious to have prevented its acceptance as a preferred way of making a CCD imager. This, in spite of the fact that theoretically this type of CCD imager should be preferred over CCD imagers of the popular field transfer and interline transfer types having similar imaging areas, because the line transfer CCD imager takes up less area on a semiconductor substrate. A principal problem arises because the clocking signals applied to a CCD imager are coupled to the charge sensing stage, by means of capacitance between the substrate and the points of signal application. This charge sensing stage typically is an electrometer, the floating diffusion type of electrometer being favored for its low noise.
The floating-diffusion electrometer employs an insulated-gate field effect transistor (FET) with its gate electrode connected to a floating diffusion in a charge transfer channel. The FET has a conduction channel between its source and drain electrodes that has conductance proportional to the voltage at its gate, which is proportional to the magnitude of the charge packet under the floating diffusion. The FET conductance controls current flow through the FET conduction channel for determining the amplitudes of samples generated in the voltage or current regime as electrometer output.
The electrostatic coupling of clocking voltages to the gate electrode of the electrometer FET places voltage variations on that gate electrode which are appreciably large, as compared to the gate voltage induced responsive to the magnitude of the charge packet under the floating diffusion. As long as the clocking voltages coupled to the gate electrode of the electrometer FET recur regularly at the sampling rate at which the electrometer is operated, they heterodyne with the electrometer sampling rate to zero frequency and to harmonics of electrometer sampling rate in the video signal output taken from the CCD imager. Within the baseband, these portions of the frequency spectrum only affect the direct-voltage pedestal on which rides the video signal taken from the CCD imager. This pedestal is discarded in the normal black level clamping and dc-restoration processes in the video processing amplifier used after the CCD imager.
However, variation from the regular recurrence of clocking signal electrostatically coupled to the electrometer FET gate electrode, as occurs during a change in the one(s) of the line-transfer register charge transfer channels selected for forward clocking, heterodynes with the electrometer sample rate to cause disturbances in the baseband frequencies of the video signal and to generate spectra around the harmonics of electrometer sampling rate. This gives rise to undesirable line-selection artifacts in the video signal output. Line-selection artifacts attributable to selection of line-transfer register charge transfer channel(s) for forward clocking, appear as a diagonal line disturbance across television pictures derived from the video output signals of CCD imagers using side-loaded CCD shift registers to transfer charge packets from their line-transfer registers to charge sensing stages that employ floating-diffusion or floating-gate electrometers. This line-selection artifact problem has been described in detail by P. K. Weimer in his U.S. patent application Ser. No. 688,982, filed Jan. 4, 1985, entitled "REMOVAL OF LINE SELECTION ARTIFACTS FROM TRACE PORTIONS OF LINE TRANSFER CCD IMAGER OUTPUT SIGNALS", and assigned to RCA Corporation.
A portion of the diagonally disposed line-selection artifacts falls within line retrace intervals and does not disrupt the television picture that is painted on the kinescope screen during successive line trace intervals. Artifacts attributable to selection of line-transfer register charge transfer channels for forward clocking can be made to fall completely within the line retrace intervals. Ways of doing this in line transfer types of CCD imager are described by P. K. Weimer in U.S. patent application Ser. No. 688,982.
One way described by Weimer replaces the side-loaded CCD shift register with an end-loaded CCD shift register. This end-loaded CCD shift register has a charge transfer channel with an input port wide enough to connect to the parallel output ports of the line-transfer register charge transfer channels, and with an output port relatively narrow compared to its input port to boost the sensitivity of the electrometer connected thereafter. The charge transfer stages between the input and output ports of this charge transfer channel are sufficient in number to delay charge packets for a time interval longer than line trace interval, but shorter than 1H. The video response from a electrometer connected after this or end-loaded CCD shift register exhibits line-selection artifacts in a line that is perpendicular to line scan and, having no appreciable dimension along scan line, can be fitted entirely within line retrace intervals. There are limitations, imposed by the need for efficient charge transfer, on the rate at which the width of the charge transfer channel of the end-loaded charge transfer channel can converge. These limitations undesirably cause the end-loaded CCD shift register to take up appreciable area on the CCD imager die. Weimer overcomes this problem in part by partitioning the line-transfer register, apportioning its charge transfer channels among bands of adjacent charge transfer channels, and by using a separate end-loaded CCD shift register to connect the output ports of each band of line-transfer register charge transfer channels to the electrometer.
Weimer also describes in his patent application another way of placing the line-selection artifacts entirely within the line retrace intervals. It uses a variable-length clocked CCD delay line before the charge sensing stage of the CCD imager, to compensate for the differential delay introduced by using a parallelly loaded CCD imager.
The line selection artifacts are made to be in a line perpendicular to the direction of line scan, rather than skewed respective to the direction of line scan, in both these ways for putting line-selection artifacts entirely within line retrace intervals. Weimer avoids the use of side-loaded CCD shift registers, which give rise to a line of line-selection artifacts askew line scan, despite side-loaded CCD shift registers being a way of commutating charge packets out of the image register that is economical of imager die area and of clocking power.
In the prior art CCD imagers using line-transfer registers, the differential delay introduced by the side-loaded shift register is typically 240 or 480 pixel scan durations. This is because there are about 480 active lines in a television picture using a 525-line standard. The side-loaded CCD shift register has one charge transfer stage for each line-transfer register charge transfer channel or pair of adjacent line-transfer register charge transfer channels; and the clock rate of the side-loaded CCD shift register is the same as the selected line-transfer register charge transfer channel, which is forward clocked at pixel scan rate. The prior art imagers with line-transfer registers use only 200 to 400 pixels per line trace interval portion of line scan. Since line retrace interval is typically one sixth of 1H, line retrace interval is one-fifth the length of line trace in number of pixel durations. For a line trace interval of 200 to 400 pixel durations, line retrace interval is 40 to 80 pixel durations. So the diagonal line-selection artifact, 240 to 480 pixels wide in the direction of line scan, perforce extends past line retrace interval and over most of the active picture area described by the CCD imager output signal.
As time passes, however, the spatial resolution desired in CCD imagers increases. CCD imagers of the field transfer type have been proposed which have 768 pixels in each scan line trace portion. It is desirable to make the number of pixels per scan line a multiple of 192 for an NTSC camera since there are an integral number of pixels per cycle of the color subcarrier. (Favorable numbers of pixels per line trace interval exist for other color broadcast standards, such as PAL.) The trend is eventually to a standard of 1536 pixels per line trace interval. At the same time, the number of scan lines per frame may increase to 1050 or so in the television camera, even when only 525 lines are actually broadcast. With the trend towards higher resolution in CCD imagers, the line transfer type of imager becomes increasingly attractive.
Increasing the spatial resolution in the direction of charge transfer channel length is preferable to increasing it in the direction of charge transfer channel width, since the latter way of increasing resolution is accompanied by loss of charge handling capability to additional channel-stop and anti-blooming-drain structure. Furthermore, the increase in resolution along the length of the channel is governed by the degree of overlap of successive gates, rather than by gate electrode length per se, which puts less demand on the photolithographic processes determining pixel size. Accordingly, line transfer image registers facilitate increasing spatial resolution along the scan line direction, and they are to be preferred where the number of scan lines is not increased more than a very few times, in seeking to afford better resolution in the direction perpendicular to scan lines. The limitations of photolithography place constraints on the minimum pixel size in an imager; therefore, increasing the number of pixels per field tends to increase minimum imager size. So the smaller die size available with a line transfer imager becomes more important when one wishes to maximize the number of imagers per wafer of semiconductor material. It is easier to spatially multiplex the read-out of a line transfer imager, to bring out in parallel responses from different portions of the image register, than it is to spatially multiplex the read-out of a field transfer CCD imager or an interline transfer CCD imager transferring perpendicular to line scan. Such spatial multiplexing reduces clocking rates to reduce clocking signal dissipation that heats up the CCD imager.
The greater number of pixels per scan line trace interval increases the number of pixel durations in scan line retrace interval. There are approximately 154 pixel scan durations in line retrace when there are 768 pixel scan durations in line trace; and there are approximately 307 pixel scan durations line retrace when there are 1536 pixel scan durations in line trace. So a diagonal line artifact much wider in the line scan direction in terms of pixels scan durations can be accommodated in the line retrace intervals. Suppose one could shorten, by a small factor, the differential delay in a side-loaded CCD shift register used to transfer charge packets from the image register of a line transfer CCD imager to its electrometer. If the differential delay were shortened four times, for example, then the diagonal line-selection artifact could be caused to fall entirely within the line retrace intervals, in these line transfer CCD imagers with a large number of pixels per scan line.
The same is true for CCD imagers of horizontal interline transfer type. These CCD imagers are representative of a class of imager in which the line transfer register is not used as an image register, as in the line transfer CCD imager, but in which the line transfer register is used as a temporary field storage register. Although the mechanisms for putting charge packets into their line transfer registers are different in the line-transfer and horizontal-interline-transfer types of CCD imager, the problems of transferring the charge packets out of their line transfer registers to their charge sensing stages are identical.
It is also desirable to keep diagonal line artifacts out of line trace intervals in the video output signal from a horizontal-field-transfer type of CCD imager. In this type of imager the charge transfer channels in an image register are aligned parallel to, not perpendicular with, the direction of line scanning. Each charge transfer channel in the image register has its output port connected to the input port of a corresponding charge transfer channel in a line-transfer register. During field retrace intervals this type of imager transfers the field of charge packets, which were formed the previous field trace interval by photoconversion of image elements, from its image register into the line-transfer register, which is masked from light. The image register may be shuttered during field transfer to eliminate transfer smear. Then, during the ensuing field trace interval the line-transfer register is read in the same way as in the line-transfer type of imager.
The present inventor describes other ways of placing the line-selection artifacts entirely with line retrace intervals, in his U.S. patent application Ser. No. 824,556 entitled "CCD CIRCUITRY FOR LINE-SEQUENTIAL READ OUT OF A PHOTOSENSOR ARRAY", filed Jan. 23, 1986, and assigned to RCA Corporation. One way the present inventor describes replaces the one CCD shift register side-loaded in respective charge transfer stages from all the lines in the line-transfer register with a plurality of CCD shift registers each having a reduced number of charge transfer stages, each side-loaded in its respective charge transfer stages from only a restricted number of the lines in the image register. The number of lines side-loading each shift register is restricted sufficiently that the differential delay experienced by those lines is sufficiently small that the diagonally disposed line-selection artifacts fall entirely within line retrace intervals.
Another way the present inventor describes uses one output CCD shift register into which the charge transfer channels of the line transfer register successively clocked out their charge packets to be conveyed through the output CCD shift register to the charge sensing stage. The number of charge transfer stages in this output CCD shift register is reduced, replacing sets of short-length charge transfer stages with single long-length charge transfer stages, respectively. Each long-length charge transfer stage is loaded not from one image register charge transfer channel, but several of them. The output CCD shift register continues to be forward clocked at pixel scan rate, to advance charge packets one charge transfer stage per pixel read out from image register, but the reduced number of charge transfer stages in the output CCD shift register reduces the differential delay through it from its various side-loading input ports.
In this disclosure, the present inventor describes the reduction of differential delay through the output CCD shift register by increasing its forward clock rate from pixel scan rate to a multiple of pixel scan rate.